This invention relates to a semiconductor device, and more particularly to a semiconductor device including a bipolar transistor.
The switching speed and power dissipation of a semiconductor device, which are the basic standards for indicating its performance, are determined by the value of the current in the transistor employed therein, and by the electrostatic capacitance of the elements, including parasitic elements, whose charge and discharge must be made with this current. It is desirable that the value of this capacitance be as small as possible, because the power required to operate the transistor is proportional to the capacitance for a given current. In addition, the capacitance must be reduced in order to increase the switching speed of the transistor, because the RC time constant of the transistor is proportional to the capacitance for a given sheet resistance.
Some of the present inventors have developed a semiconductor device including a bipolar transistor, etc., whose power dissipation is small, which operates at a high speed, and wherein the elements occupy a small area, by isolating the active region, etc., of the semiconductor from the substrate thereof by an insulation film, thereby reducing a parasitic capacitance, and they have already filed a patent application therefor (Japanese Patent Laid-Open No. 56-1556 and U.S. patent application No. 158,366).
FIG. 1 is a section through the structure of one example of this semiconductor device. The following is a description thereof, and it is to be noted the material of each part and the conductivity types of the semiconductor layers are prescribed (the first conductivity type is taken to be n-type and the second conductivity type to be p-type) therein so as to simplify the explanation. This also applies to the description of the present invention which follows later. Needless to say, the invention is not limited to the materials and conductivity types used for explanation purposes.
In FIG. 1, numeral 1 denotes an Si substrate of p-type conductivity, 2 a buried layer of n.sup.+ -type conductivity, and 3, 4 (4.sub.-1, 4.sub.-2, 4.sub.-3 and 4.sub.-4) and 5 epitaxially-grown Si layers of which 3 is an n-type conductivity region, 4 a p-type conductivity region, and 5 an n.sup.+ -type conductivity region. Each of these regions is formed by the doping of impurities. Numeral 6 denotes an insulation film, 7 a polycrystalline semiconductor layer, 8 an insulation film, and 9 an electrode. Numeral (I) denotes a lateral bipolar transistor wherein the electrodes of emitter and collector regions (4.sub.-1 and 4.sub.-2) are taken out through the polycrystalline semiconductor layer 7 between the insulation films 6 and 8. Numeral (II) denotes a vertical bipolar transistor wherein the electrodes of base regions (an intrinsic base region 4-3 and a graft base region 4.sub.-4) are also taken out through the polycrystalline semiconductor layer 7 between the insulation films 6 and 8.
The structure of the transistors shown in FIG. 1 has the advantages that it enables high-speed operation because of their small parasitic capacitance, and that it also enables a reduction of the area of the elements. However, the resistance thereof is not reduced, since the take-out electrodes from the active region formed of a monocrystalline layer are constituted by the polycrystalline semiconductor layer 7. Accordingly, although the time constant, expressed as the product of the resistance and the capacitance, is reduced by the effect of the reduction of the parasitic capacitance, the realization of high-speed operation is hindered in a circuit wherein a number of multi-emitter structures are used, since the speed of operation is determined by the time constant of the slowest emitter. This is because the time constant of each emitter is affected by the resistance of the polycrystalline semiconductor layer.
Monocrystalline p-type conductivity regions 4 (4.sub.-1, 4.sub.-2 and 4.sub.-4) in contact with the polycrystalline semiconductor layer 7 are formed by the diffusion of the p-type impurities from the polycrystalline semiconductor layer 7. That is, the p-type graft base region 4.sub.-4 is formed by diffusion from an unstable polycrystalline semiconductor region with a different diffusion constant, due to differences in the process conditions. This makes it difficult to control the depth of the graft base, and thus it has been difficult to manufacture an element with an emitter (n.sup.+ -type region 5) of a small area.